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general description the max4358 is a 32 ? 16 highly integrated video crosspoint switch matrix with input and output buffers and on-screen display (osd) insertion. this device operates from dual ?v to ?v supplies or from a sin- gle +5v supply. digital logic is supplied from an inde- pendent single +2.7v to +5.5v supply. individual outputs can be switched between an input video signal source and osd information through an internal, dedi- cated fast 2:1 mux (40ns switching times) located before the output buffer. all inputs and outputs are buffered, with all outputs able to drive standard 75 ? reverse-terminated video loads. the switch matrix configuration and output buffer gain are programmed through an spi/qspi-compatible, three-wire serial interface and initialized with a single update signal. the unique serial interface operates in two modes facilitating both fast updates and initializa- tion. on power-up, all outputs are initialized in the dis- abled state to avoid output conflicts in large-array configurations. superior flexibility, high integration, and space-saving packaging make this nonblocking switch matrix ideal for routing video signals in security and video-on- demand systems. the max4358 is available in a 144-pin tqfp package and specified over an extended -40? to +85? tem- perature range. the max4358 evaluation kit is available to speed designs. applications security systems video routing video-on-demand systems features ? 32 ? 16 nonblocking matrix with buffered inputs and outputs ? operates from a ?v, ?v, or +5v supply ? fast switching (40ns) 2:1 osd insertion mux ? each output individually addressable ? individually programmable output buffer gain (a v = +1v/v or +2v/v) ? high-impedance output disable for wired-or connections ? 0.1db gain flatness to 12mhz ? minimum -62db crosstalk, -110db isolation at 6mhz ? 0.05%/0.1 differential gain/differential phase error ? low 195mw power consumption (0.38mw per point) max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ________________________________________________________________ maxim integrated products 1 ordering information 19-2111; rev 0; 8/01 evaluation kit available part temp range pin package max4358ece -40? to +85? 144 tqfp pin configuration appears at end of data sheet. spi/qspi are trademarks of motorola, inc. out0 osdfill0 osdkey0 osdfill1 osdkey1 osdfill15 osdkey15 out1 out15 in0 cameras in1 in31 monitor monitor monitor max4358 osd generator for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. typical operating circuit max4358 32 x 16 switch matrix power-on reset serial interface thermal shutdown decode logic disable all outputs latches 512 16 16 matrix register 112 bits update register 16 bits 2:1 osd mux enable/disable a v * a v * a v * a v * *a v = +1v/v or +2v/v a0-a3 mode in0 in1 in2 in31 din sclk update ce reset osdkey0 osdkey15 osdkey1 osdfill0 osdfill15 out0 out1 out2 out15 v cc v ee dgnd v dd dout aout osdfill1 agnd functional diagram
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics?ual supplies ?v (v cc = +5v, v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in _= 0, v osdfill _ = 0, r l = 150 ? to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog supply voltage (v cc - v ee ) .....................................+11v digital supply voltage (v dd - dgnd) ...................................+6v analog supplies to analog ground (v cc - agnd) and (agnd - v ee ) ..................................... +6v analog ground to digital ground .........................-0.3v to +0.3v in__, osdfill__ voltage range .... (v cc + 0.3v) to (v ee - 0.3v) out__ short-circuit duration to agnd, v cc , or v ee ....indefinite sclk, ce , update , mode, a_, din, dout, reset , aout , osdkey__..........(v dd + 0.3v) to (dgnd - 0.3v) current into any analog input pin (in_, osdfill_).........?0ma current into any analog output pin (out_).....................?5ma continuous power dissipation (t a = +70?) 144-pin tqfp (derate 28.6mw/? above +70?).........2.23w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) ................................ +300? parameter symbol conditions min typ max units operating supply voltage range v cc - v ee guaranteed by psrr test 4.5 10.5 v logic supply voltage range v dd to dgnd 2.7 5.5 v (v ee + 2.5v) < v in _ < (v cc - 2.5v), a v = +1v/v, r l = 150 ? 0.97 0.995 1 (v ee + 2.5v) < v in _ < (v cc - 2.5v), a v = +1v/v, r l = 10k ? 0.99 0.999 1 (v ee + 3.75v) < v in _ < (v cc - 3.75v), a v = +2v/v, r l = 150 ? 1.92 1.996 2.08 (v ee + 3.75v) < v in _ < (v cc - 3.75v) a v = +2v/v, r l = 10k ? 1.94 2.008 2.06 gain (note 1) a v (v ee + 1v) < v in _ < (v cc - 1.2v), a v = +1v/v, r l = 10k ? 0.95 0.994 1 v/v r l = 10k ? 0.5 1.5 gain matching (channel to channel) r l = 150 ? 0.5 2 % temperature coefficient of gain tc av 10 ppm/ c r l = 10k ? v e e + 1 v c c - 1.2 a v = +1v/v r l = 150 ? v e e + 2.5 v c c - 2.5 r l = 10k ? v ee + 3 v c c - 3.1 input voltage range v in _ a v = +2v/v r l = 150 ? v e e + 3.75 v c c - 3.75 v
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers _______________________________________________________________________________________ 3 dc electrical characteristics?ual supplies ?v (continued) (v cc = +5v, v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in _= 0, v osdfill _ = 0, r l = 150 ? to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units r l = 10k ? v ee + 1 v c c - 1.2 v output voltage range v out r l = 150 ? v e e + 2.5 v c c - 2.5 v input bias current i b 4 11 a input resistance r in _ (v ee + 1v) < v in _ < (v cc - 1.2v) 10 m ? a v = +1v/v ? ?0 output offset voltage v offset a v = +2v/v ?0 ?0 mv output short-circuit current i sc sinking or sourcing, r l = 1 ? ?0 ma enabled output impedance z out (v ee + 1v) < v in _ < (v cc - 1.2v) 0.2 ? output leakage current, disable mode i od (v ee + 1v) < v out _ < (v cc - 1.2v) 0.004 1 a dc power-supply rejection ratio psrr 4.5v < (v cc - v ee ) < 10.5v 60 70 db outputs enabled, t a = +25 c 110 160 outputs enabled 185 i cc r l = outputs disabled 60 80 outputs enabled, t a = +25 c 105 160 outputs enabled 185 i ee r l = outputs disabled 55 80 quiescent supply current i dd 4 8 ma
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 4 _______________________________________________________________________________________ dc electrical characteristics?ual supplies ?v (v cc = +3v, v ee = -3v, v dd = +3v, agnd = dgnd = 0, v in _ = 0, v osdfill _ = 0, r l = 150 ? to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units operating supply voltage range v cc - v ee guaranteed by psrr test 4.5 10.5 v logic supply voltage range v dd to dgnd 2.7 5.5 v (v ee + 1v) < v in _ < (v cc - 1.2v), a v = +1v/v, r l = 150 ? 0.94 0.983 1 (v ee + 1v) < v in _ < (v cc - 1.2v), a v = +1v/v, r l = 10k ? 0.96 0.993 1 (v ee + 2v) < v in _ < (v cc - 2.1v), a v = +2v/v, r l = 150 ? 1.92 1.985 2.08 gain (note 1) a v (v ee + 2v) < v in _ < (v cc - 2.1v) a v = +2v/v, r l = 10k ? 1.94 2.00 2.06 v/v r l = 10k ? 0.5 1.5 gain matching (channel to channel) r l = 150 ? 0.5 2 % temperature coefficient of gain tc av 10 ppm/ c r l = 10k ? v ee + 1 v cc - 1.2 a v = +1v/v r l = 150 ? v ee + 1 v cc - 1.2 r l = 10k ? v ee + 2 v cc - 2.1 input voltage range v in _ a v = +2v/v r l = 150 ? v ee + 2 v cc - 2.1 v r l = 10k ? v ee + 1 v cc - 1.2 output voltage range v out r l = 150 ? v ee + 1 v cc - 1.2 v input bias current i b 4 11 ? input resistance r in (v ee + 1v) < v in _ < (v cc - 1.2v) 10 m ? a v = +1v/v ? ?0 output offset voltage v offset a v = +2v/v ?0 ?0 mv
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers _______________________________________________________________________________________ 5 dc electrical characteristics?ual supplies ?v (continued) (v cc = +3v, v ee = -3v, v dd = +3v, agnd = dgnd = 0, v in _ = 0, v osdfill _ = 0, r l = 150 ? to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units output short-circuit current i sc sinking or sourcing, r l = 1 ? ?0 ma enabled output impedance z out (v ee + 1v) < v in _ < (v cc - 1.2v) 0.2 ? output leakage current, disable mode i od (v ee + 1v) < v out _ < (v cc - 1.2v) 0.004 1 ? dc power-supply rejection ratio psrr 4.5v < (v cc - v ee ) < 10.5v 60 75 db outputs enabled 95 i cc r l = outputs disabled 50 outputs enabled 90 i ee r l = outputs disabled 45 quiescent supply current i dd 3 ma dc electrical characteristics?ingle supply +5v (v cc = +5v, v ee = 0, v dd = +5v, agnd = dgnd = 0, v in _ = v osdfill _ = +1.75v, a v = +1v/v, r l = 150 ? to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units operating supply voltage range v cc guaranteed by psrr test 4.5 5.5 v logic-supply voltage range v dd to dgnd 2.7 5.5 v (v ee + 1v) < v in < (v cc - 2.5v), a v = +1v/v, r l = 150 ? 0.94 0.995 1 gain (note 1) a v (v ee + 1v) < v in < (v cc - 1.2v), a v = +1v/v, r l = 10k ? 0.94 0.995 1 v r l = 10k ? 0.5 3 gain matching (channel to channel) r l = 150 ? 0.5 3 % temperature coefficient of gain tc av 10 ppm/ c r l = 10k ? v ee + 1 v cc - 1.2 input voltage range v in a v = +1v/v r l = 150 ? v ee + 1 v cc - 2.5 v a v = +1v/v, r l = 10k ? v ee + 1 v cc - 1.2 output voltage range v out a v = +1v/v, r l = 150 ? v ee + 1 v cc - 2.5 v
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units input bias current i b 4 11 ? input resistance r in v ee + 1v < v in < v cc - 1.2v 10 m ? output offset voltage v offset a v = +1v/v ?0 ?0 mv output short-circuit current i sc sinking or sourcing, r l = 1 ? ?5 ma enabled output impedance z out (v ee + 1v) < v in < (v cc - 1.2v) 0.2 ? output leakage current, disable mode i od (v ee + 1v) < v out _ < (v cc - 1.2v) 0.004 1 ? dc power-supply rejection ratio psrr 4.5v < v cc - v ee < 5.5v 50 65 db outputs enabled, t a = +25 c 85 i cc r l = outputs disabled 35 outputs enabled, t a = +25 c 80 i ee r l = outputs disabled 30 quiescent supply current i dd 4 ma dc electrical characteristics?ingle supply +5v (continued) (v cc = +5v, v ee = 0, v dd = +5v, agnd = dgnd = 0, v in _ = v osdfill _ = +1.75v, a v = +1v/v, r l = 150 ? to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.)
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers _______________________________________________________________________________________ 7 parameter symbol conditions min typ max units v dd = +5.0v 3 input voltage high level v ih v dd = +3v 2 v v dd = +5.0v 0.8 input voltage low level v il v dd = +3v 0.6 v excluding reset -1 0.01 1 input current high level i ih v i > 2v reset -30 -20 a excluding reset -1 0.01 1 input current low level i il v i < 1v reset -300 -235 a i source = 1ma, v dd = +5v 4.7 4.9 output voltage high level v oh i source = 1ma, v dd = +3v 2.7 2.9 v i sink = 1ma, v dd = +5v 0.1 0.3 output voltage low level v ol i sink = 1ma, v dd = +3v 0.1 0.3 v v dd = +5v, v o = +4.9v 1 4 output current high level i oh v dd = +3v, v out = +2.7v 1 8 ma v dd = +5v, v o = +0.1v 1 4 output current low level i ol v dd = +3v, v o = +0.3v 1 8 ma logic-level characteristics (v cc - v ee) = +4.5v to +10.5v, v dd = +2.7v to +5.5v, agnd = dgnd = 0, v in _ = v osdfill _ = 0, r l = 150 ? to agnd, and t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) ac electrical characteristics?ual supplies ?v (v cc = +5v, v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in _ = v osdfill _ = 0, r l = 150 ? to agnd, and t a = +25?, unless other- wise noted.) parameter symbol conditions min typ max units a v = +1v/v 95 small-signal -3db bandwidth bw ss v out_ = 20mvp-p a v = +2v/v 70 mhz a v = +1v/v 90 medium-signal -3db bandwidth bw ms v out_ = 200mvp-p a v = +2v/v 70 mhz a v = +1v/v 40 large-signal -3db bandwidth bw ls v out_ = 2vp-p a v = +2v/v 50 mhz a v = +1v/v 15 small-signal 0.1db bandwidth bw 0.1db-ss v out_ = 20mvp-p a v = +2v/v 15 mhz a v = +1v/v 15 medium-signal 0.1db bandwidth bw 0.1db-ms v out_ = 200mvp-p a v = +2v/v 15 mhz a v = +1v/v 12 large-signal 0.1db bandwidth bw 0.1db-ls v out_ = 2vp-p a v = +2v/v 12 mhz v out_ = 2v step, a v = +1v/v 150 slew rate sr v out_ = 2v step, a v = +2v/v 160 v/ s
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 8 _______________________________________________________________________________________ ac electrical characteristics?ual supplies ?v (v cc = +3v, v ee = -3v, v dd = +3v, agnd = dgnd = 0, v in _= v osdfill _ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units a v = +1v/v 60 settling time t s 0.1% v out_ = 0 to 2v step a v = +2v/v 60 ns a v = +1v/v 50 switching transient (glitch) (note 3) a v = +2v/v 50 mv f = 100khz 70 ac power-supply rejection ratio f = 1mhz 68 db r l = 1k ? 0.01 differential gain error (note 4) r l = 150 ? 0.05 % r l = 1k ? 0.03 differential phase error (note 4) r l = 150 ? 0.1 d eg r ees crosstalk, all hostile f = 6mhz -62 db off-isolation, input-to-output f = 6mhz -110 db input noise voltage density e n bw = 6mhz 73 v rms input capacitance c in 5 pf disabled output capacitance amplifier in disable mode 3 pf capacitive load at 3db output peaking 30 pf output enabled 3 output impedance z out f = 6mhz output disabled 4k ? parameter symbol conditions min typ max units a v = +1v/v 90 small-signal -3db bandwidth bw ss v out _ = 20mvp-p a v = +2v/v 65 mhz a v = +1v/v 90 medium-signal -3db bandwidth bw ms v out _ = 200mvp-p a v = +2v/v 65 mhz a v = +1v/v 30 large-signal -3db bandwidth bw ls v out _ = 2vp-p a v = +2v/v 35 mhz a v = +1v/v 15 small-signal 0.1db bandwidth bw 0.1db-ss v out_ = 20mvp-p a v = +2v/v 15 mhz a v = +1v/v 15 medium-signal 0.1db bandwidth bw 0.1db-ms v out _ = 200mvp-p a v = +2v/v 15 mhz a v = +1v/v 12 large-signal 0.1db bandwidth bw 0.1db-ls v out _ = 2vp-p a v = +2v/v 12 mhz ac electrical characteristics?ual supplies ?v (continued) (v cc = +5v, v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in _ = v osdfill _ = 0, r l = 150 ? to agnd, and t a = +25?, unless other- wise noted.)
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers _______________________________________________________________________________________ 9 parameter symbol conditions min typ max units v out _ = 2v step a v = +1v/v 120 slew rate sr v out _ = 2v step a v = +2v/v 120 v/ s a v = +1v/v 60 settling time t s 0.1% v o = 0 to 2v step a v = +2v/v 60 ns a v = +1v/v 15 switching transient (glitch) (note 3) a v = +2v/v 20 mv f = 100khz 60 ac power-supply rejection ratio f = 1mhz 40 db r l = 1k ? 0.03 differential gain error (note 4) r l = 150 ? 0.2 % r l = 1k ? 0.08 differential phase error (note 4) r l = 150 ? 0.2 d eg r ees crosstalk, all hostile f = 6mhz -63 db off-isolation, input to output f = 6mhz -112 db input noise voltage density e n bw = 6mhz 73 v rms input capacitance c in _ 5 pf disabled output capacitance amplifier in disable mode 3 pf capacitive load at 3db output peaking 30 pf output enabled 3 output impedance z out f = 6mhz output disabled 4k ? ac electrical characteristics?ual supplies ?v (continued) (v cc = +3v, v ee = -3v, v dd = +3v, agnd = dgnd = 0, v in _= v osdfill _ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless otherwise noted.)
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 10 ______________________________________________________________________________________ parameter symbol conditions min typ max units small-signal -3db bandwidth bw ss v out_ = 20mvp-p 90 mhz medium-signal -3db bandwidth bw ms v out = 200mvp-p 90 mhz large-signal -3db bandwidth bw ls v out = 1.5vp-p 38 mhz small-signal 0.1db bandwidth bw 0.1db-ss v out = 20mvp-p 12 mhz medium-signal 0.1db bandwidth bw 0.1db-ms v out _ = 200mvp-p 12 mhz large-signal 0.1db bandwidth bw 0.1db-ls v out_ = 1.5vp-p 12 mhz slew rate sr v out _ = 2v step, a v = +1v/v 100 v/ s settling time t s 0.1% v out _ = 0 to 2v step 60 ns switching transient (glitch) 25 mv f = 100khz 70 ac power-supply rejection ratio f = 1mhz 69 db r l = 1k ? 0.03 differential gain error (note 4) r l = 150 ? 0.15 % r l = 1k ? 0.06 differential phase error (note 4) r l = 150 ? 0.2 d eg r ees crosstalk, all hostile f = 6mhz -63 db off-isolation, input-to- output f = 6mhz -110 db input noise voltage e n bw = 6mhz 73 v rms input capacitance c in _ 5 pf disabled output capacitance amplifier in disable mode 3 pf capacitive load at 3db output peaking 30 pf output enabled 3 output impedance z out f = 6mhz output disabled 4k ? ac electrical characteristics?ingle supply +5v (v cc = +5v, v ee = 0, v dd = +5v, agnd = dgnd = 0, v in _ = v osdfill _ = 1.75v, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless otherwise noted.)
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 11 switching characteristics ((v cc - v ee ) = +4.5v to +10.5v, v dd = +2.7v to +5.5v, dgnd = agnd = 0, v in _ = v osdfill _ = 0 for dual supplies, v in _ = v osdfill _ = +1.75v for single supply, r l = 150 ? to agnd, c l = 100pf, a v = +1v/v, and t a = t min - t max , unless otherwise noted. typical values are at t a = +25?. ) note 1: associated output voltage may be determined by multiplying the input voltage by the specified gain (a v ) and adding output offset voltage. gain is specified for in_ and osdfill_ signal paths. note 2: logic level characteristics apply to the following pins: din, dout, sclk, ce , update , reset , a3?0, mode, aout , and osdkey_. note 3: switching transient settling time is guaranteed by the settling time (t s ) specification. switching transient is a result of updat- ing the switch matrix. note 4: input test signal: 3.58mhz sine wave of amplitude 40ire superimposed on a linear ramp (0 to 100ire). ire is a unit of video-signal amplitude developed by the international radio engineers: 140ire = 1.0v. note 5: all devices are 100% production tested at +25?. specifications over temperature limits are guaranteed by design. parameter symbol conditions min typ max units delay: update to video out t pdudvo v in = 0.5v step 200 450 ns delay: update to aout t pdudao mode = 0, time to aout = low after update = low 30 200 ns v dd = +5v 40 delay: osdkey_ to output t pdokvo/ t pdofvo v out = 0.5v step v dd = +3v 60 ns delay: sclk to dout valid t pddo logic state change in dout on active sclk edge 30 200 ns delay: output disable t pdhoevo v out = 0.5v, 1k ? pulldown to agnd 300 800 ns delay: output enable t pdloevo output disabled, 1k ? pulldown to agnd, v in = 0.5v 200 800 ns setup: ce to sclk t suce 100 ns setup: din to sclk t sudi 100 ns hold time: sclk to din t hddi 100 ns minimum high time: sclk t mnhck 100 ns minimum low time: sclk t mnlck 100 ns minimum low time: update t mnlud 100 ns setup time: update to sclk t suhud rising edge of update to falling edge of sclk 100 ns hold time: sclk to update t hdhud falling edge of sclk to falling edge of update 100 ns setup time: mode to sclk t sumd minimum time from clock edge to mode with valid data clocking 100 ns hold time: mode to sclk t hdmd minimum time from clock edge to mode with valid data clocking 100 ns minimum low time: reset t mnlrst 300 ns delay: reset t pdrst 10k ? pulldown to agnd 600 ns
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 12 ______________________________________________________________________________________ symbol type description ao signal address valid flag ( aout ) ce signal clock enable ( ce ) ck signal clock (sclk) di signal serial data in (din) do signal serial data output (dout) md signal mode oe signal output enable rst signal reset input ( reset ) ud signal update vo signal video out (out) h property high- or low-to-high transition hd property hold l property low- or high-to-low transition mn property minimum mx property maximum pd property propagation delay su property setup tr property transition w property width naming conventions: all parameters with time units are given ??designation, with appropriate subscript modifiers. propagation delays for clocked signals are from active edge of clock. propagation delay for level sensitive signals is from input to output at 50% point of a transition. setup and hold times are measured from 50% point of sig- nal transition to 50% point of clocking signal transition. ?setup time refers to any signal that must be stable before active clock edge, even if signal is not latched or clocked itself. ?hold time refers to any signal that must be stable during and after active clock edge, even if signal is not latched or clocked. ?propagation delays to unobservable internal signals are modified to setup and hold designations applied to observ- able io signals. symbol definitions
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 13 data and control timing osd: key and fill timing ce: ce ck: sclk of: osdfill i in_ video source (selected input) video output (with superimposed osd) out i ok: osdkey i di: din do: dout ud: update vo: out_ rst: reset oe: output enable ao: aout t suce t hdce t mnhck t mnlck t sudi t hddi t pddo t hdud t mnlud t suud t pdhokvo t pdlofvo t pdlokvo hi-z t pdudvo t wtrvo t pdudao t pdrstvo t mulrst t pdhoevo t pdloevo hi-z timing parameter definitions name description t pdudvo delay: update to video out t pdudao delay: update to aout t pdokvo delay: osd key to video output t pdofvo delay: osd fill to video output t pddo delay: clk to data out t pdhoevo delay: output enable to video output (high: disable) t pdloevo delay: output enable to video output (low: enable) t suce setup: clock enable to clock t sudi setup time: data in to clock timing parameter definitions name description t hddi hold time: clock to data in t mnhck min high time: clk t mnlck min low time: clk t mnlud min low time: update t suhud setup time: update to clk with update high not valid setup time: update to clk with update low t hdhud hold time: clk to update with update high not valid hold time: clk to update with update low t pddido asynchronous delay: data in to data out t mnmd min low time: mode t mxtr max rise time: clk, update t mnlrst min low time: reset t pdrstvo delay: reset to video output figure 1. timing diagram timing diagram
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 14 ______________________________________________________________________________________ typical operating characteristics?ual supplies ?v (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25 c, unless otherwise noted.) 3 -7 0.1 1 10 100 1000 large-signal frequency response -5 max4358 toc01 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 ? a v = +1v/v a v = +2v/v 3 -7 0.1 1 10 100 1000 medium-signal frequency response -5 max4358 toc02 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 ? a v = +1v/v a v = +2v/v 3 -7 0.1 1 10 100 1000 small-signal frequency response -5 max4358 toc03 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 ? a v = +2v/v a v = +1v/v 3 -7 0.1 1 10 100 1000 large-signal frequency response -5 max4358 toc04 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 1k ? a v = +2v/v a v = +1v/v 3 -7 0.1 1 10 100 1000 medium-signal frequency response -5 max4358 toc05 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 1k ? a v = +1v/v a v = +2v/v 3 -7 0.1 1 10 100 1000 small-signal frequency response -5 max4358 toc06 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 1k ? a v = +2v/v a v = +1v/v 0.7 -0.3 0.1 1 10 100 1000 large-signal gain flatness vs. frequency -0.1 max4358 toc07 frequency (mhz) normalized gain (db) 0.1 0.3 0.5 0.4 0.2 0.0 -0.2 0.6 a v = +2v/v a v = +1v/v 0.1 1 10 100 1000 large-signal gain flatness vs. frequency max4358 toc08 frequency (mhz) normalized gain (db) 0.3 -0.7 -0.5 -0.3 -0.1 0.1 0.0 -0.2 -0.4 -0.6 0.2 r l = 1k ? a v = +2v/v a v = +1v/v 0.1 1 10 100 1000 large-signal frequency response (a v = +1v/v) max4358 toc09 frequency (mhz) normalized gain (db) 3 7 5 3 1 1 0 2 4 6 2 c l = 30pf c l = 45pf c l = 15pf
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 15 typical operating characteristics?ual supplies ?v (continued) (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25 c, unless oth- erwise noted.) 0.1 1 10 100 1000 large-signal frequency response (a v = +2v/v) max4358 toc10 frequency (mhz) normalized gain (db) 3 7 5 3 1 1 0 2 4 6 2 c l = 30pf c l = 45pf c l = 15pf 0.1 1 10 100 1000 medium-signal frequency response (a v = +1v/v) max4358 toc11 frequency (mhz) normalized gain (db) 9 -1 1 3 5 7 6 4 2 0 8 c l = 30pf c l = 45pf c l = 15pf 0.1 1 10 100 1000 medium-signal frequency response (a v = +2v/v) max4358 toc12 frequency (mhz) normalized gain (db) 7 -3 -1 1 3 5 4 2 0 -2 6 c l = 30pf c l = 45pf c l = 15pf -40 -100 0.1 10 100 1 1000 max4358 toc13 frequency (mhz) crosstalk (db) -90 -80 -70 -60 -50 crosstalk vs. frequency a v = +1v/v -40 -90 0.1 1 10 100 1000 crosstalk vs. frequency -80 max4358 toc14 frequency (mhz) crosstalk (db) -70 -60 -50 -55 -65 -75 -85 -45 a v = +2v/v 0 -100 0.1 1 10 100 1000 distortion vs. frequency -80 max4358 toc15 frequency (mhz) distortion (dbc) -60 -40 -20 -30 -50 -70 -90 -10 a v = +1v/v 2 nd harmonic 3 nd harmonic 0 -100 0.1 1 10 100 1000 distortion vs. frequency -80 max4358 toc16 frequency (mhz) distortion (dbc) -60 -40 -20 -30 -50 -70 -90 -10 a v = +2v/v 2 nd harmonic 3 nd harmonic 0.1 10 1 100 1000 enabled-output impedance vs. frequency max4358 toc17 frequency (mhz) output impedance ( ? ) 1000 0.1 1 10 100 0.1 10 1 100 1000 disabled output impedance vs. frequency max4358 toc18 frequency (mhz) output impedance ( ? ) 1m 1 10 10k 1k 100 100k
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 16 ______________________________________________________________________________________ typical operating characteristics?ual supplies ?v (continued) (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless otherwise noted.) -40 -50 -60 -70 -80 -90 -100 -110 -120 100k 10m 100m 1m 1g max4358 toc19 frequency (hz) off isolation (db) off isolation vs. frequency 10k 1m 100k 10m 100m power-supply rejection ratio vs. frequency max4358 toc20 frequency (hz) psrr (db) -75 -70 -60 -65 -55 -50 1000 10 10 10k 100k 1m 100 1k 10m input voltage noise vs. frequency 100 frequency (hz) voltage noise (nv hz) max4358 toc21 large-signal pulse response (a v = +1v/v) max4358 toc22 20ns/div input 1v/div output 1v/div large-signal pulse response (a v = +2v/v) max4358 toc23 20ns/div input 500mv/div output 1v/div medium-signal pulse response (a v = +1v/v) max4358 toc24 20ns/div input 100mv/div output 100mv/div medium-signal pulse response (a v = +2v/v) max4358 toc25 20ns/div input 50mv/div output 100mv/div switching time (a v = +1v/v) max4358 toc26 20ns/div v update 5v/div v out 500mv/div switching time (a v = +2v/v) max4358 toc27 20ns/div v update 5v/div v out 1v/div
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 17 typical operating characteristics?ual supplies ?v (continued) (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless otherwise noted.) switching transient (glitch) (a v = +1v/v) max4358 toc28 20ns/div v update 5v/div v out 25mv/div switching transient (glitch) (a v = +2v/v) max4358 toc29 20ns/div v update 5v/div v out 25mv/div 0 100 50 200 150 250 300 -14 -10 -8 -6 -12 -4 -2 0 2 4 6 offset voltage distribution max4358 toc30 offset voltage (mv) -0.05 0102030405060708090100 0102030405060708090100 differential gain and phase vs. dc voltage (r l = 150 ? ) 0.00 0.00 -0.02 0.05 0.02 0.04 0.10 0.06 0.08 0.15 ire diff phase ( ) diff gain (%) max4358 toc31 0.01 0.00 -0.01 0102030405060708090100 0102030405060708090100 differential gain and phase vs. dc voltage (r l = 1k ? ) 0.02 -0.005 0.03 0.000 0.005 0.04 0.010 0.015 0.05 ire diff phase ( ) diff gain (%) max4358 toc32 large-signal pulse response with capacitive load (c l = 30pf, a v = +1v/v) max4358 toc33 20ns/div input 1v/div output 1v/div large-signal pulse response with capacitive load (c l = 30pf, a v = +2v/v) max4358 toc34 20ns/div input 500mv/div output 1v/div medium-signal pulse response with capacitive load (c l = 30pf, a v = +1v/v) max4358 toc35 20ns/div input 100mv/div output 100mv/div medium-signal pulse response with capacitive load (c l = 30pf, a v = +2v/v) max4358 toc36 20ns/div input 50mv/div output 100mv/div
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 18 ______________________________________________________________________________________ typical operating characteristics?ual supplies ?v (continued) (v cc = +5v and v ee = -5v, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless oth- erwise noted.) -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -50 0 -25 255075100 gain vs. temperature max4358 toc37 temperature (?) normalized gain (db) a v = +2v/v a v = +1v/v 1p 10n 1 100p 10p 1n 100n 10 100 max4358 toc38 10n 10 1 100n 100 1m 10m 100m 10 1 reset delay vs. c reset reset delay (s) c reset (f) osd switching transient (100ire level switch) (a v = +2v/v) max4358 toc39 50ns/div v osdkey0 5v/div v out0 500mv/div 100ire 0ire osd switching 3.58mhz signal (a v = +2v/v) max4358 toc40 50ns/div v osdkey0 5v/div v out0 500mv/div 0 20 10 40 30 60 50 70 -50 0 25 -25 50 75 100 supply current vs. temperature max4358 toc41 temperature ( c) supply current (ma) i cc i ee i dd
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 19 typical operating characteristics?ual supplies ?v (v cc = +3v and v ee = -3v, v dd = +3v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless otherwise noted.) 3 -7 0.1 1 10 100 1000 large-signal frequency response -5 max4358 toc42 frequency (mhz) normalized gain (db) -3 -1 1 -0 -2 -4 -6 2 a v = +2v/v r l = 150 ? a v = +1v/v 3 -7 0.1 1 10 100 1000 medium-signal frequency response -5 max4358 toc43 frequency (mhz) normalized gain (db) -3 -1 1 -0 -2 -4 -6 2 a v = +2v/v r l = 150 ? a v = +1v/v 3 -7 0.1 1 10 100 1000 small-signal frequency response -5 max4358 toc44 frequency (mhz) normalized gain (db) -3 -1 1 -0 -2 -4 -6 2 a v = +2v/v r l = 150 ? a v = +1v/v 3 -7 0.1 1 10 100 1000 large-signal frequency response -5 max4358 toc45 frequency (mhz) normalized gain (db) -3 -1 1 -0 -2 -4 -6 2 a v = +1v/v r l = 1k ? a v = +2v/v 3 -7 0.1 1 10 100 1000 medium-signal frequency response -5 max4358 toc46 frequency (mhz) normalized gain (db) -3 -1 1 -0 -2 -4 -6 2 a v = +1v/v r l = 1k ? a v = +2v/v 3 -7 0.1 1 10 100 1000 small-signal frequency response -5 max4358 toc47 frequency (mhz) normalized gain (db) -3 -1 1 -0 -2 -4 -6 2 a v = +2v/v r l = 1k ? a v = +1v/v 0.9 -0.1 0.1 1 10 100 1000 large-signal gain flatness vs. frequency 0.1 max4358 toc48 frequency (mhz) normalized gain (db) 0.3 0.5 0.7 0.6 0.4 0.2 0 0.8 a v = +1v/v a v = +2v/v 0.6 -0.4 0.1 1 10 100 1000 large-signal gain flatness vs. frequency -0.2 max4358 toc49 frequency (mhz) normalized gain (db) 0.0 0.2 0.4 0.3 0.1 -0.1 -0.3 0.5 r l = 1k ? a v = +2v/v a v = +1v/v 3 -7 0.1 1 10 100 1000 large-signal frequency response (a v = +1v/v) -5 max4358 toc50 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 c l = 15pf c l = 30pf c l = 45pf
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 20 ______________________________________________________________________________________ typical operating characteristics?ual supplies ?v (continued) (v cc = +3v and v ee = -3v, v dd = +3v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless oth- erwise noted.) -30 -80 100k 1m 10m 100m 1g crosstalk vs. frequency -70 max4358 toc55 frequency (hz) crosstalk (db) -60 -50 -40 -45 -55 -65 -75 -35 a v = + 2v/v -100 -80 -60 -40 -20 -30 -50 -70 -90 -10 100k 100m 10m 1m distortion vs. frequency max4358 toc56 frequency (hz) distortion (db) a v = + 1v/v 2 nd harmonic 3 rd harmonic -100 -80 -60 -40 -20 -30 -50 -70 -90 -10 100k 100m 10m 1m distortion vs. frequency max4358 toc57 frequency (hz) distortion (db) a v = + 2v/v 2 nd harmonic 3 rd harmonic 0.1 10 1 100 1000 enabled output impedance vs. frequency max4358 toc58 frequency (mhz) output impedance ( ? ) 1000 0.1 1 10 100 1m 1 0.1 10 100 1 1000 disabled output impedance vs. frequency max4358 toc59 frequency (mhz) output impedance ( ? ) 10 100 1k 10k 100k 3 -7 0.1 1 10 100 1000 large-signal frequency response (a v = +2v/v) -5 max4358 toc51 frequency (mhz) normalized gain (db) -3 -1 1 -0 -2 -4 -6 2 c l = 30pf c l = 15pf c l = 45pf 9 1 0.1 1 10 100 1000 medium-signal frequency response 1 max4358 toc52 frequency (mhz) normalized gain (db) 3 5 7 6 4 2 0 8 (a v = +1v/v) c l = 15pf c l = 30pf c l = 45pf 7 -3 0.1 1 10 100 1000 medium-signal frequency response -1 max4358 toc53 frequency (mhz) normalized gain (db) 1 3 5 4 2 0 -2 6 (a v = +2v/v) c l = 30pf c l = 15pf c l = 45pf -40 -90 100k 1m 10m 100m 1g crosstalk vs. frequency -80 max4358 toc54 frequency (hz) crosstalk (db) -70 -60 -50 -55 -65 -75 -85 -45 a v = + 1v/v
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 21 typical operating characteristics?ual supplies ?v (continued) (v cc = +3v and v ee = -3v, v dd = +3v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25 c, unless otherwise noted.) -40 -50 -60 -70 -80 -90 -100 -110 -120 100k 10m 100m 1m 1g off isolation vs. frequency max4358 toc60 frequency (hz) off isolation (db) 10k 1m 100k 10m 100m power-supply rejection ratio vs. frequency max4358 toc61 frequency (hz) psrr (db) -50 -75 -70 -60 -65 -55 1000 10 10 10k 100k 1m 100 1k 10m input voltage noise vs. frequency 100 max4358 toc62 frequency(hz) voltage noise (nv/ hz) large-signal pulse response (a v = +1v/v) max4358 toc63 input 1v/div output 1v/div 20ns/div large-signal pulse response (a v = +2v/v) max4358 toc64 input 500mv/div output 1v/div 20ns/div medium-signal pulse response (a v = +1v/v) max4358 toc65 input 100mv/div output 100mv/div 20ns/div medium-signal pulse response (a v = +2v/v) max4358 toc66 input 50mv/div output 100mv/div 20ns/div switching time (a v = +1v/v) max4358 toc67 v out 500mv/div 20ns/div v update 3v/div switching time (a v = +2v/v) max4356 toc68 v out 1v/div v update 3v/div 20ns/div
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 22 ______________________________________________________________________________________ typical operating characteristics?ual supplies ?v (continued) (v cc = +3v and v ee = -3v, v dd = +3v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless otherwise noted.) 0.05 -0.05 0.15 10 30 40 50 20 60 70 80 90 100 differential gain and phase (r l = 1k ? ) max4358 toc73 ire differential gain (%) differential phase ( ) 0.05 -0.05 0.15 0.25 20ns/div large-signal pulse response with capacitive load (c l = 30pf, a v = +1v/v) input 1v/div output 1v/div max4358 toc74 20ns/div large-signal pulse response with capacitive load (c l = 30pf, a v = +2v/v) input 500mv/div output 1v/div max4358 toc75 20ns/div medium-signal pulse response with capacitive load (c l = 30pf, a v = +1v/v) input 100mv/div output 100mv/div max4358 toc76 20ns/div medium-signal pulse response with capacitive load (c l = 30pf, a v = +2v/v) input 50mv/div output 100mv/div max4358 toc77 50 0 150 100 250 200 300 -15 -11 -9 -7 -13 -5 -3 -1 1 3 5 offset voltage distribution max4358 toc71 offset voltage (mv) 20ns/div switching transient glitch (a v = +1v/v) v update 3v/div v out 25mv/div max4358 toc69 20ns/div switching transient glitch (a v = +2v/v) v update 3v/div v out 25mv/div max4358 toc70 0.05 -0.05 0.15 0.25 10 30 40 50 20 60 70 80 90 100 differential gain and phase (r l = 150 ? ) max4358 toc72 ire differential gain (%) differential phase ( ) 0.05 -0.05 0.15 0.25
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 23 typical operating characteristics?ual supplies ?v (continued) (v cc = +3v and v ee = -3v, v dd = +3v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless otherwise noted.) 50ns/div osd switching 3.58mhz signal v osdkey0 3v/div v out0 500mv/div max4358 toc81 a v = +2v/v -50 0 -25 255075100 gain vs. temperature max4356 toc78 temperature ( c) normalized gain (db) -0.20 -0.15 -0.05 -0.10 0.10 0.15 0.05 0.20 0 a v = +2v/v a v = +1v/v 1p 10n 1 100p 10p 1n 100n 10 100 max4356 toc79 10n 10 1 100n 100 1m 10m 100m 10 1 reset delay vs. c reset reset delay (s) c reset (f) 50ns/div osd switching transient (100ire level switch) v osdkey0 3v/div v out0 500mv/div max4358 toc80 100ire 0ire a v = +2v/v
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 24 ______________________________________________________________________________________ 3 -7 0.1 1 10 100 1000 small-signal frequency response -5 max4358 toc87 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 1k ? 0.9 -0.1 0.1 1 10 100 1000 large-signal gain flatness vs. frequency 0.1 max4358 toc88 frequency (mhz) normalized gain (db) 0.3 0.5 0.7 0.6 0.4 0.2 0.0 0.8 0.6 -0.4 0.1 1 10 100 1000 large-signal gain flatness vs. frequency -0.2 max4358 toc89 frequency (mhz) normalized gain (db) 0 0.2 0.4 0.3 0.1 -0.1 -0.3 0.5 r l = 1k ? 3 -7 0.1 1 10 100 1000 large-signal frequency response (a v = +1v/v) -5 max4358 toc90 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 c l = 30pf c l = 15pf c l = 45pf 3 -7 0.1 1 10 100 1000 large-signal frequency response -5 max4358 toc82 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 ? 3 -7 0.1 1 10 100 1000 medium-signal frequency response -5 max4358 toc83 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 ? 3 -7 0.1 1 10 100 1000 small-signal frequency response -5 max4358 toc84 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 150 ? 3 -7 0.1 1 10 100 1000 large-signal frequency response -5 max4358 toc85 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 1k ? 3 -7 0.1 1 10 100 1000 medium-signal frequency response -5 max4358 toc86 frequency (mhz) normalized gain (db) -3 -1 1 0 -2 -4 -6 2 r l = 1k ? typical operating characteristics?ingle supply +5v (v cc = +5v and v ee = 0, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless oth- erwise noted.)
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 25 typical operating characteristics?ingle supply +5v (continued) (v cc = +5v and v ee = 0, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25 c, unless oth- erwise noted.) 9 -1 0.1 1 10 100 1000 medium-signal frequency response (a v = +1v/v) 1 max4358 toc91 frequency (mhz) normalized gain (db) 3 5 7 6 4 2 0 8 c l = 30pf c l = 15pf c l = 45pf -50 -100 100k 1m 10m 100m 1g crosstalk vs. frequency -90 max4358 toc92 frequency (hz) crosstalk (db) -80 -70 -60 -65 -75 -85 -95 -55 -10 -100 100k 100m 10m 1m distortion vs. frequency -70 -90 -30 -50 0 -60 -80 -20 -40 max4358 toc93 frequency (hz) distortion (dbc) 2nd harmonic 3rd harmonic 0.1 10 1 100 1000 enabled output impedance vs. frequency max4358 toc94 frequency (mhz) output impedance ( ? ) 1000 0.1 1 10 100 1m 1 0.1 10 100 11000 disabled output impedance vs. frequency max4358 toc95 frequency (mhz) output impedance ( ? ) 10 100 1k 10k 100k -40 -50 -60 -70 -80 -90 -100 -110 -120 100k 10m 100m 1m 1g off isolation vs. frequency max4358 toc96 frequency (hz) off isolation (db) 10k 1m 100k 10m 100m power-supply rejection ratio vs. frequency max4358 toc97 frequency (hz) psrr (db) -50 -75 -70 -60 -65 -55 1000 10 10 10k 100k 1m 100 1k 10m input voltage noise vs. frequency 100 max4358 toc98 frequency (hz) voltage noise (nv/ hz) 20ns/div large-signal pulse response input 1v/div output 1v/div max4358 toc99
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 26 ______________________________________________________________________________________ typical operating characteristics?ingle supply +5v (continued) (v cc = +5v and v ee = 0, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless oth- erwise noted.) 20ns/div medium-signal pulse response input 100mv/div output 100mv/div max4358 toc100 20ns/div switching time v update 5v/div v out 500mv/div max4358 toc101 20ns/div switching transient (glitch) v update 5v/div v out 25mv/div max4358 toc102 0 50 150 100 200 250 -20 -16 -18 -14 -8 -10 -12 -6 -4 -2 0 offset voltage histogram max4358 toc103 offset voltage (mv) ire differential gain and phase (r l = 150 ? ) differential gain (%) differential phase (%) max4358 toc104 0.25 0.20 0.15 0.10 0.05 0 -0.05 0.30 0.25 0.20 0.15 0.10 0 -0.05 -0.10 10 20 30 40 50 60 70 80 90 100 ire differential gain and phase (r l = 1k ? ) differential gain (%) differential phase (%) max4358 toc105 0.04 0.03 0.02 0.01 0 -0.01 0.10 0.08 0.06 0.04 0.02 0 -0.02 10 20 30 40 50 60 70 80 90 100
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 27 typical operating characteristics?ingle supply +5v (continued) (v cc = +5v and v ee = 0, v dd = +5v, agnd = dgnd = 0, v in_ = 0, r l = 150 ? to agnd, a v = +1v/v, and t a = +25?, unless oth- erwise noted.) 1p 10n 1 100p 10p 1n 100n 10 100 reset delay vs. c reset max4358 toc109 c reset (f) reset delay (s) 10n 100m 1 10 100 10m 1m 100 10 1 100n 50ns/div osd switching 3.58mhz signal v osdkey0 5v/div v out0 250mv/div max4358 toc111 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -50 0 -25 25 50 75 100 gain vs. temperature max4358 toc108 temperature ( c) normalized gain (db) 50ns/div osd switching transient (100ire level switch) v osdkey0 5v/div v out0 250mv/div max4358 toc110 100ire 0ire 20ns/div medium-signal pulse response with capacitive load (c l = 30pf) input 100mv/div output 100mv/div max4358 toc107 20ns/div large-signal pulse response with capacitive load (c l = 30pf) input 1v/div input 1v/div max4358 toc106
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 28 ______________________________________________________________________________________ pin description pin name function 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 127, 129, 131, 133, 135, 137, 139, 141, 143 in0?n31 buffered analog inputs 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 72, 73, 107, 108, 109, 126, 128, 130, 132, 134, 136, 138, 140, 142 agnd analog ground 36, 74, 78, 82, 86, 90, 94, 98, 102, 106 v cc positive analog supply. bypass each pin with a 0.1? capacitor to agnd. connect a single 10? capacitor from one v cc pin to agnd. 38, 40, 42, 44 a3?0 address programming inputs. connect to dgnd or v dd to select the address for individual output address mode. see table 4. 46 dgnd digital ground 47 aout address recognition output. aout drives low after successful chip address recognition. 48 mode serial interface mode select input. drive high for complete matrix mode (mode 1), or drive low for individual output address mode (mode 0). 49 din serial data input. data is clocked-in on the falling edge of sclk. 50 sclk serial clock input 51 update update input. drive update low to transfer data from mode registers to the switch matrix. 52 reset asynchronous reset input/output. drive reset low to initiate hardware reset. all analog outputs are disabled. additional power-on reset delay may be set by connecting a small capacitor from reset to dgnd. 53 ce clock enable input. drive low to enable the serial data interface. 54 dout serial data output. in complete matrix mode, data is clocked through the 112- bit matrix control shift register. in individual output address mode, data at din passes directly to dout. 55?0 osdkey0 osdkey15 digital control input. control for the fast 2:1 osd insertion multiplexer routing signal to output buffers. a logic high routes programmed in_ analog input signal to output buffer. a logic low routes the dedicated osdfill_ input to corresponding output buffer. 71 v dd digital logic supply. bypass v dd with a 0.1? capacitor to dgnd. 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105 out0 out15 buffered analog outputs. gain is individually programmable for a v = +1v/v or a v = +2v/v via the serial interface. outputs may be individually disabled (high impedance). on power-up, or assertion of reset , all outputs are disabled. 76, 80, 84, 88, 92, 96, 100, 104, 144 v ee negative analog supply. bypass each pin with a 0.1? capacitor to agnd. connect a single 10? capacitor from one v ee pin to agnd. 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125 osdfill15 ?sdfill0 dedicated osd analog signal buffered inputs. for each output buffer amplifier. osdfill i input signal is routed to output buffer amplifier out i when the corresponding osdkey i is low.
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 29 detailed description the max4358 is a highly integrated 32 ? 16 nonblock- ing video crosspoint switch matrix . all inputs and out- puts are buffered, with all outputs able to drive standard 75 ? reverse-terminated video loads. a three-wire interface programs the switch matrix and initializes with a single update signal. the unique serial interface operates in one of two modes, complete matrix mode (mode 1) or individual output address mode (mode 0). the signal path of the max4358 is from the buffered inputs (in0?n31), through the switching matrix, buffered by the output amplifiers, and presented at the outputs (out0?ut15) ( functional diagram ). the other functional blocks are the serial interface and con- trol logic. each of the functional blocks is described in detail below. analog outputs the max4358 outputs are high-speed amplifiers capa- ble of driving 150 ? (75 ? back-terminated) loads. the gain, a v = +1v/v or +2v/v, is selectable via program- ming bit 5 of the serial control word. amplifier compen- sation is automatically optimized to maximize the bandwidth for each gain selection. each output can be individually enabled and disabled via bit 6 of the serial control word. when disabled, the output is high imped- ance presenting typically 4k ? load, and 3pf output capacitance, allowing multiple outputs to be connected together for building large arrays. on power-up (or asynchronous reset ) all outputs are initialized in the disabled state to avoid output conflicts in large array configurations. the programming and operation of the max4358 is output referred. outputs are configured individually to connect to any one of the 32 analog inputs, programmed to the desired gain (a v = +1v/v or +2v/v), and enabled or disabled in a high-impedance state. max4358 32 x 16 switch matrix power-on reset serial interface thermal shutdown decode logic disable all outputs latches 512 16 16 matrix register 112 bits update register 16 bits 2:1 osd mux enable/disable a v * a v * a v * a v * *a v = +1v/v or +2v/v a0-a3 mode in0 in1 in2 in31 din sclk update ce reset osdkey0 osdkey15 osdkey1 osdfill0 osdfill15 out0 out1 out2 out15 v cc v ee dgnd v dd dout aout osdfill1 agnd functional diagram
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 30 ______________________________________________________________________________________ table 1. operation truth table ce update sclk din dout mode aout reset operation/comments 1 x x x x x x 1 no change in logic 01 d i d i-112 11 1 data at din is clocked on negative edge of sclk into 112- bit complete matrix mode register. dout supplies original data in 112 sclk pulses later. 00 x x x 1 1 1 data in serial 112-bit complete matrix mode register is transferred into parallel latches which control the switching matrix. 01 d i d i 01 1 data at din is routed to individual output address mode shift register. din is also connected directly to dout so that all devices on the serial bus may be addressed in parallel. 00 x d i d i 00 1 4-bit chip address a3?0 is compared to d14?11. if equal, remaining 11 bits in individual output address mode register are decoded, allowing reprogramming for a single output. aout signals successful individual matrix update. xx xx xxx 0 asynchronous reset. all outputs are disabled. other logic remains unchanged. analog inputs the max4358 offers 32 analog input channels. each input is buffered before the crosspoint matrix switch, allowing one input to cross-connect up to 16 outputs. the input buffers are voltage feedback amplifiers with high-input impedance and low input bias current. this allows the use of very simple input clamp circuits. osdfill and osdkey inputs intended for on-screen display insertion, the 16 osd- fill inputs are buffered analog signal inputs that are routed to a dedicated output buffer through a fast 2:1 mux. the signal presented to the output buffer is selected from the programmed analog input signal (in_) and the dedicated osdfill input signal. switch matrix the max4358 has 512 individual t-switches making a 32 ? 16 switch matrix. the switching matrix is 100% nonblocking, which means that any input may be rout- ed to any output. the switch matrix programming is output-referred. each output may be connected to any one of the 32 analog inputs. any one input can be rout- ed to all 16 outputs with no signal degradation. digital interface the digital interface consists of the following pins: din, dout, sclk, aout , update , ce , a3?0, mode, and reset . din is the serial-data input, dout is the serial- data output. note: "x" = don? care
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 31 sclk is the serial-data clock which clocks data into the data input registers (figure 3). data at din is loaded in at each falling edge of sclk. dout is the data shifted out of the 112-bit complete matrix mode register (mode = 1). din passes directly to dout when in individual output address mode (mode = 0). the falling edge of update latches the data and pro- grams the matrix. when using individual output address mode, the address recognition output aout drives low when control-word bits d14 to d11 match the address programming inputs (a3?0) and update is low (table 1). table 1 is the operation truth table. programming the matrix the max4358 offers two programming modes: individual output address mode and complete matrix mode. these two distinct programming modes are selected by toggling a single mode pin high or low. both modes operate with the same physical board lay- out. this flexibility allows initial programming of the ic by daisy-chaining and sending one long data word while still being able to immediately address and update individual outputs in the matrix. individual output address mode (mode = 0) drive mode to logic low to select mode 0. individual outputs are programmed via the serial interface with a single 16-bit control word. the control word consists of a don? care msb, the chip address bits, output address bits, an output enable/disable bit, an output gain-set bit, and input address bits (table 2 through table 6, and figure 2). 16-bit individual output address mode register 112-bit complete matrix mode register output address decode mode mode data routing gate a b s mode switch matrix output enable dout switch decode din sclk mode ce sclk mode ce update en a0?3 chip address aout 4 4 11 11 7 112 112 1 7 112 512 16 112-bit parallel latch figure 2. serial interface block diagram
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 32 ______________________________________________________________________________________ in mode 0, data at din passes directly to dout through the data routing gate (figure 3). in this configu- ration, the 16-bit control word is simultaneously sent to all chips in an array of up to 16 addresses. complete matrix mode (mode = 1) drive mode to logic high to select mode 1. a single 112-bit control word, consisting of sixteen 7-bit control words, programs all outputs. the 112-bit control word? first 7-bit control word (msbs) programs output 15, and the last 7-bit control word (lsbs) programs output 0 (table 7 and figures 4 and 5). data clocked into the 112-bit complete matrix mode register is latched on the falling edge of update , and the outputs are immedi- ately updated. initialization string complete matrix mode (mode = 1) is convenient for programming the matrix at power-up. in a large matrix consisting of many max4358s, all the devices can be programmed by sending a single bit stream equal to n x 112 bits where n is the number of max4358 devices on the bus. the first 112-bit data word programs the last in-line max4358 (see matrix programming under the applications information section). on-screen-display (osd) fast mux the max4358 features an asynchronous dedicated 2:1 mux for each output buffer amplifier. fast 40ns switch- ing times enable pixel switching for on-screen-display (osd) information such as text or other picture-in-pic- ture signals (figure 1). osdfill_ inputs are buffered analog inputs connected to each dedicated osd mux. drive the dedicated osdkey_ digital input to switch between the programmed in_ input from the crosspoint switch matrix and the osdfill_. a logic low on osdkeyi routes the analog signal at osdfilli to the outi output buffer. osdkey_ control does not affect the crosspoint switch matrix programming or the out- put-buffer enable/disable or gain-set programming. reset the max4358 features an asynchronous bidirectional reset with an internal 20k ? pullup resistor to v dd . when reset is pulled low either by internal circuitry, or driven externally, the analog output buffers are latched into a high-impedance state. after reset is released, the output buffers remain disabled. the outputs may be enabled by sending a new 112-bit data word or a 16-bit individual output address word. a reset is initiated from any of three sources. reset can be driven low by external circuitry to initiate a reset, or reset can be pulled low by internal circuitry during power-up (power- on-reset) or thermal shutdown. table 2. 16-bit serial control word bit assignments (mode 0: individual output address mode) bit name function 15 (msb) x don? care 14 ic address a3 msb of selected chip address 13 ic address a2 12 ic address a1 11 ic address a0 lsb of selected chip address 10 output address b3 msb of output buffer address 9 output address b2 8 output address b1 7 output address b0 lsb of output buffer address 6 output enable enable bit for output, 0 = disable, 1 = enable. 5 gain set gain select for output buffer, 0 = gain of +1v/v, 1 = gain of +2v/v. 4 input address 4 msb of input channel select address 3 input address 3 2 input address 2 1 input address 1 0 (lsb) input address 0 lsb of input channel select address
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 33 since driving reset low only clears the output-buffer- enable bit in the matrix control latches, reset can be used to disable all outputs simultaneously. if no new data has been loaded into the 112-bit complete matrix mode register, a single update restores the previous matrix control settings. power-on-reset the power-on-reset ensures all output buffers are in a disabled state when power is initially applied. a v dd voltage comparator generates the power-on-reset. when the voltage at v dd is less than 2.5v, the power- on-reset comparator pulls reset low via internal cir- cuitry. as the digital-supply voltage ramps up crossing 2.5v, the max4358 holds reset low for 40ns (typ). connecting a small capacitor from reset to dgnd extends the power-on-reset delay. (see the power-on- reset vs. reset capacitance graph in typical operating characteristics) . thermal shutdown the max4358 features thermal shutdown protection with temperature hysteresis. when the die temperature exceeds 150?, the max4358 pulls reset low, dis- abling the output buffer. when the die cools by 20?, the reset pulldown is deasserted, and output buffers remain disabled until the device is programmed again. applications information building large video-switching systems the max4358 can be easily used to create larger switching matrices. the number of ics required to implement the matrix is a function of the number of input channels, the number of outputs required, and whether the array needs to be nonblocking or not. input address 0 (lsb) = 0 output enable input address 1 = 0 input address 4 (msb) = 1 gain set = +1v/v input address 2 = 0 input address 3 = 0 sclk din example of 16-bit serial control word for output control in individual output address mode output (i) enabled, a v = +1v/v, connected to input 16 update output address b0 output address b1 output address b2 output address b3 ic address a0 ic address a1 ic address a2 ic address a3 ic address = 2 output address = 9 mode 16-bit individual output address mode: first bit is a don't care bit, last 15 bits clocked into din when mode = 0, creates address word; ic address a3?0 is compared to din14?in11 when update is low; if equal, addressed output is updated don't care x t sumd t hdmd figure 3. mode 0, individual output address mode timing and programming example
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 34 ______________________________________________________________________________________ t mnlud t suhud t hddi t sudi t mnhck t mnlck input address 0 (lsb) = 0 enable output input address 1 = 0 input address 4 (msb) = 1 gain set = +1v/v input address 2 = 1 input address 3 = 1 sclk din sclk update dout t pddo din example of 7-bit serial control word for output control next control word output (i) enabled, a v = +1v/v, connected to input 28 most significant bits of the 7-bit control word are shifted in first; i.e. out15, then out14, etc. last 7 bits shifted in prior to update falling edge program out0. time out2 out1 out0 din update 7-bit control word 1 0 mode 1 0 figure 5. mode 1: complete matrix mode programming figure 4. 7-bit control word and programming example (mode 1: complete matrix mode)
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 35 table 3. chip address programming for 16-bit control word (mode 0: individual output address mode) ic address bit address a3 (msb) a2 a1 a0 (lsb) chip address (hex) chip address (decimal) 0 0 0 0 0h 0 0 0 0 1 1h 1 0 0 1 0 2h 2 0 0 1 1 3h 3 0 1 0 0 4h 4 0 1 0 1 5h 5 0 1 1 0 6h 6 0 1 1 1 7h 7 1 0 0 0 8h 8 1 0 0 1 9h 9 1 0 1 0 ah 10 1 0 1 1 bh 11 1 1 0 0 ch 12 1 1 0 1 dh 13 1 1 1 0 eh 14 1 1 1 1 fh 15 table 4. chip address a3?0 pin programming pin address a3 a2 a1 a0 chip address (hex) chip address (decimal) dgnd dgnd dgnd dgnd 0h 0 dgnd dgnd dgnd v dd 1h 1 dgnd dgnd v dd dgnd 2h 2 dgnd dgnd v dd v dd 3h 3 dgnd v dd dgnd dgnd 4h 4 dgnd v dd dgnd v dd 5h 5 dgnd v dd v dd dgnd 6h 6 dgnd v dd v dd v dd 7h 7 v dd dgnd dgnd dgnd 8h 8 v dd dgnd dgnd v dd 9h 9 v dd dgnd v dd dgnd ah 10 v dd dgnd v dd v dd bh 11 v dd v dd dgnd dgnd ch 12 v dd v dd dgnd v dd dh 13 v dd v dd v dd dgnd eh 14 v dd v dd v dd v dd fh 15
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 36 ______________________________________________________________________________________ the most straightforward technique for implementing nonblocking matrices is to arrange the building blocks in a grid. the inputs connect to each vertical bank of devices in parallel with the other banks. the outputs of each building block in a vertical column connect together in a wired-or configuration. figure 6.shows a 128-input, 32-output, nonblocking array using eight max4358 crosspoint devices. the wire-or connection of the outputs shown in the diagram is possible because the outputs of the ic devices can be placed in a disabled, or high-imped- ance-output state. this disable state of the output buffers is designed for a maximum impedance vs. fre- quency while maintaining a low output capacitance. these characteristics minimize the adverse loading effects from the disabled outputs. larger arrays are constructed by extending this connection technique to more devices. driving a capacitive load figure 6 shows an implementation requiring many out- puts to be wired together. this creates a situation where each output buffer sees not only the normal load impedance, but also the disabled impedance of all the other outputs. this impedance has a resistive and a capacitive component. the resistive components reduce the total effective load for the driving output. table 5. output selection programming output address bit b3 (msb) b2 b1 b0 (lsb) selected output 0 000 0 0 001 1 0 010 2 0 011 3 0 100 4 0 101 5 0 110 6 0 111 7 1 000 8 1 001 9 1 010 10 1 011 11 1 100 12 1 101 13 1 110 14 1 111 15 inputs (0?1) outputs (16?1) 32 in 16 out 32 in 16 out 32 in 16 out 32 in 16 out max4358 max4358 max4358 max4358 inputs (32?3) inputs (64?5) inputs (96?27) 32 in 16 out 32 in 16 out 32 in 16 out 32 in 16 out max4358 max4358 max4358 max4358 outputs (0?5) figure 6. 128 x 32 nonblocking matrix using 32 x 16 crosspoint devices
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 37 total capacitance is the sum of the capacitance of all the disabled outputs and is a function of the size of the matrix. also, as the size of the matrix increases, the length of the pc board traces increases, adding more capacitance. the output buffers have been designed to drive more than 30pf of capacitance while still main- taining a good ac response. depending on the size of the array, the capacitance seen by the output can exceed this amount. there are several ways to improve the situation. the first is to use more building-block crosspoint devices to reduce the number of outputs that need to be wired together (see figure 7). in figure 7, the additional devices are placed in a sec- ond bank to multiplex the signals. this reduces the number of wired-or connections. another solution is to put a small resistor in series with the output before the capacitive load to limit excessive ringing and oscilla- tions. figure 8 shows the graph of the optimal isolation table 6. input selection programming input address bit b4 (msb) b3 b2 b1 b0 (lsb) selected input 00000 0 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 29 11110 30 11111 31 inputs (0?1) inputs (32?3)) inputs (64?5) inputs (96?27) outputs (0?5) 32 in 16 out 32 in 16 out 32 in 16 out 32 in 16 out 16 in 16 in 16 out max4358 max4358 max4358 max4358 max4358 figure 7. 128 x 16 nonblocking matrix with reduced capacitive loading 0 10 5 20 15 25 30 0 500 optimal isolation resistance vs. capacitive load capacitive load (pf) isolation resistance ( ? ) 200 100 300 400 figure 8. optimal isolation resistor vs. capacitive load
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 38 ______________________________________________________________________________________ resistor vs. capacitive load. a lowpass filter is created from the series resistor and parasitic capacitance to ground. a single r-c do not affect the performance at video frequencies, but in a very large system there may be many r-cs cascaded in series. the cumulative effect is a slight rolling off of the high frequencies caus- ing a "softening" of the picture. there are two solutions to achieve higher performance. one way is to design the pc board traces associated with the outputs such that they exhibit some inductance. by routing the traces in a repeating "s" configuration, the traces that are nearest each other will exhibit a mutual inductance increasing the total inductance. this series inductance causes the amplitude response to increase or peak at higher frequencies, offsetting the rolloff from the para- sitic capacitance. another solution is to add a small- value inductor to the output. on-screen display insertion the max4358 facilitates the insertion of on-screen graphics and characters by using the built-in fast 2:1 multiplexer associated with each of the 16 outputs ( functional diagram ). this mux switches in 40ns, much less than the width of a single pixel. access to this fast mux is through 16 dedicated osdfill analog inputs and 16 dedicated osdkey input controls. osd timing is externally controlled and applied to the osdkey inputs (figure 1). pulling osdkey i low switches the signal on the osdfill i input to the out i output. when the osdkey signal is logic high, the signal at in_ is switched to the output. this switching action is repeat- ed on a pixel-by-pixel basis for each scan line. in this way any synchronized video signal, including arbitrary graphics, can be inserted on the screen (figure 9). this technique for inserting osd display information is an improvement over the way it has traditionally been done. other osd techniques require an external fast mux and a buffer for each output. crosstalk and board routing issues improper signal routing causes performance problems. the max4358 has a typical crosstalk rejection of -62db at 6mhz. a bad pc board layout degrades the crosstalk rejection by 20db or more. to achieve the best crosstalk performance: 1. place ground isolation between long critical signal pc board trace runs. these traces act as a shield to potential interfering signals. crosstalk can be degraded from parallel traces as well as directly above and below on adjoining pc board layers. table 7. 7-bit serial control word bit assignments (mode 1: complete matrix mode programming) bit name function 6 (msb) output enable enable bit for output, 0 = disable, 1 = enable. 5 gain set gain select for output buffer, 0 = gain of +1v/v, 1 = gain of +2v/v. 4 input address 4 msb of input channel select address. 3 input address 3 2 input address 2 1 input address 1 0 (lsb) input address 0 lsb of input channel select address osd out0 sync0 sync1 sync0 osdfill0 osdkey0 osdfill1 osdkey1 osdfill15 osdkey15 sync1 sync15 sync15 out1 out15 in0 cameras computer control in1 in31 max4358 osd osd memory monitor monitor monitor figure 9. improved implementation of on-screen display
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 39 2.maintain controlled-impedance traces. design as many of the pc board traces as possible to be 75 ? transmission lines. this lowers the impedance of the traces reducing a potential source of crosstalk. more power will be dissipated due to the output buffer dri- ving a lower impedance. 3.minimize ground current interaction by using a good ground plane strategy. in addition to crosstalk, another key issue of concern is isolation. isolation is the rejection of undesirable feed- through from input-to-output with the output disabled. the max4358 achieves a -110db isolation at 6mhz by selecting the pinout configuration such that the inputs and outputs are on opposite sides of the package. coupling through the power supply is a function of the quality and location of the supply bypassing. use appropriate low-impedance components and locate them as close as possible to the ic. avoid routing the inputs near the outputs. power-supply bypassing the max4358 operates from a single +5v or dual ?v to ?v supplies. for single-supply operation, connect all v ee pins to ground and bypass all power-supply pins with a 0.1? capacitor to ground. for dual-supply systems, bypass all supply pins to ground with 0.1? capacitors. power in large systems t he max4358 has been designed to operate with split supplies down to ?v or a single supply of +5v. operating at the minimum supply voltages reduces the power dissipation by as much 40% to 50%. at ?v, the max4358 consumes 195mw (0.38mw/point). driving a pc-board interconnect or cable (a v = +1v/v or +2v/v) the max4358 output buffers can be programmed to either a v = +1v/v or +2v/v. the +1v/v configuration is typically used when driving short lengths (less than 3cm), high impedance, "local" pc board traces. to drive a cable or a 75 ? transmission line trace, program the gain of the output buffer to +2v/v and place a 75 ? resistor in series with the output. the series termination resistor and the 75 ? load impedance act as a voltage divider that divides the video signal in half. set the gain to +2v/v to transmit a standard 1v video signal down a cable. the series 75 ? resistor is called the back- match, reverse termination, or series termination. this 75 ? resistor reduces reflections and provides isolation, increasing the output capacitive driving capability. matrix programming the max4358? unique digital interface simplifies pro- gramming multiple max4358 devices in an array. multiple devices are connected with dout of the first host controller din sclk ce mode update dout chip address = 0 chip address = 1 virtual serial bus (mode 0: individual output address mode) chip address = 2 a3 a2 a1 a0 max4358 din sclk ce mode update dout a3 v dd a2 a1 a0 max4358 din sclk ce mode update dout next device a3 a2 a1 a0 max4358 v dd figure 10. matrix mode programming
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 40 ______________________________________________________________________________________ device connecting to din of the second device, and so on (figure 11). two distinct programming modes, individual output address mode (mode = 0) and complete matrix mode (mode = 1) are selected by toggling a single mode control pin high or low. both modes operate with the same physical board layout. this allows initial programming of the ic by daisy- chaining and sending one long data word while still being able to immediately address and update individ- ual locations in the matrix. individual output address mode (mode = 0) i n individual output address mode, the devices are connected in a serial-bus configuration, with the data routing gate (figure 3) connecting din to dout, mak- ing each device a virtual node on the serial bus. a sin- gle 16-bit control word is sent to all devices simultaneously. only the device with the corresponding chip address responds to the programming word and updates its output. in this mode the chip address is set via hardware pin strapping of a3?0. the host commu- nicates with the device by sending a 16-bit word con- sisting of 1 don? care bit, 4-chip address bits, 11 bits of data to make the word exactly two bytes in length. the 11 data bits are broken down into 4 bits to select the output to be programmed, 1 bit to set the output enable, 1 bit to set gain and 5 bits to the select the input to be connected to that output. in this method, the matrix is programmed one output at a time. complete matrix mode (mode = 1) i n complete matrix mode, the devices are connected in a daisy-chain fashion where n 5 112 bits are sent to program the entire matrix, where n = the number of max4358 devices connected in series. the data word is structured such that the first bit is the lsb of the last device in the chain and the last data bit is the msb of the first device in the chain. the total length of the data word is equal to the number of crosspoint devices to be programmed in series times 112 bits per crosspoint device. this programming method is most often used at start-up to initially configure the switching matrix. operating at +5v single-supply with a v = +1v/v or +2v/v the max4358 guarantees operation with a single +5v supply and a gain of +1v/v for standard video-input signals (1vp-p). to implement a complete video matrix switching system capable of gain = +2v/v while operat- ing with a +5v single supply, combine the max4358 crosspoint switch with maxim? low-cost, high-perfor- mance video amplifiers optimized for single +5v supply operation (figure 11). the max4450 single and max4451 dual op amps are unity-gain-stable devices that combine high-speed performance with rail-to- u2 +5v +5v agnd v ee v cc out0 out1 out15 in0 in1 in31 1v p-p 2v p-p monitor 0 75 ? 500 ? u2 = max4450 or 1/4 max4383 500 ? 75 ? z 0 = 75 ? 220 f max4358 figure 11. typical single +5v supply application
rail outputs. the common-mode input voltage range extends beyond the negative power-supply rail (ground in single-supply applications). the max4450 is avail- able in the ultra-small 5-pin sc70 package, while the max4451 is available in a space-saving 8-pin sot23 package. the max4383 is a quad op amp available in a 14-pin tssop package. the max4380/max4381/ max4382 and max4384 offer individual output-high- impedance disable making these amplifiers suitable for wired-or connections. max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers ______________________________________________________________________________________ 41 chip information transistor count: 44,890 process: bicmos rail-to-rail is a registered trademark of nippon motorola, inc.
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers 42 ______________________________________________________________________________________ top view tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 in9 agnd in10 agnd in11 agnd in12 agnd in13 agnd in14 agnd in15 agnd in16 agnd in17 agnd in18 agnd in19 agnd in20 agnd in21 agnd in22 agnd in23 agnd in24 agnd in25 agnd in26 v cc 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 agnd agnd v cc out0 v ee out1 v cc out2 v ee out3 v cc out4 v ee out5 v cc out6 v ee out7 v cc out8 v ee out9 v cc out10 v ee out11 v cc out12 v ee out13 v cc out14 v ee out15 v cc agnd 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 v ee in8 agnd in7 agnd in6 agnd in5 agnd in4 agnd in3 agnd in2 agnd in1 agnd in0 agnd osdfill0 osdfill1 osdfill2 osdfill3 osdfill4 osdfill5 osdfill6 osdfill7 osdfill8 osdfill9 osdfill10 osdfill11 osdfill12 osdfill13 osdfill14 osdfill15 agnd 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 in27 a3 in28 a2 in29 a1 in30 a0 in31 dgnd mode din sclk dout osdkey15 osdkey14 osdkey13 osdkey12 osdkey11 osdkey10 osdkey9 osdkey8 osdkey7 osdkey6 osdkey5 osdkey4 osdkey3 osdkey2 osdkey1 osdkey0 v dd agnd ce reset update aout max4358 pin configuration
max4358 32 x 16 nonblocking video crosspoint switch with on-screen display insertion and i/o buffers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 43 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information tqfp20x20x1.0mm.eps

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